An integrated circuit (IC) can be conventionally tested in a quiescent state (i.e., a sleep state), when there is no switching activity in the IC and the inputs to the IC are static. One type of quiescent state testing is known as IDDQ testing (a.k.a. quiescent current testing), in which a steady state supply current (Idd) is measured to ascertain leakage current flowing through the IC during the sleep state. IDDQ testing is a very effective test method for testing Complementary Metal-Oxide Semiconductor (CMOS) circuits, as detecting high static currents can reveal faults which cannot be found by other conventional testing methods during a powered-up state. Thus, IDDQ testing can significantly improve the quality and reliability of fabricated circuits. IDDQ testing is particularly important because IC gate counts and transistor counts are increasing, while feature size is decreasing, which lead to increases in power consumption.
IDDQ testing is based on the concept that the IC does not draw significant current when in a quiescent state. In other words, in a sleep state, only leakage current flows through the IC. When a significant leakage current flows through the device under test during a quiescent state, the leakage current indicates a manufacturing defect in the device. A defect causing the leakage current detrimentally affects the functionality of the circuit and/or the reliability of the circuit. The defect also reduces the duration of sleep time of the user product into which the device is integrated, because the leakage current drains batteries. Battery life is a key requirement for mobile devices, such as wireless communication devices.
Another way to test ICs is by using conventional automatic test pattern generation (ATPG) techniques. The ATPG techniques are typically used for testing ICs post-manufacture by applying test patterns to the IC and observing the IC's outputs. Classic ATPG scan models detect faults such as stuck-at-faults. Conventional techniques cannot perform ATPG testing, such as ATPG IDDQ testing, while the IC is in a sleep or power collapsed state.
There are long-felt industry needs to improve upon classic designs and methods, to address the aforementioned issues.